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PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
Rev. 01 -- 25 June 2002 Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM technology. Product availability: PHP71NQ03LT in SOT78 (TO-220AB) PHB71NQ03LT in SOT404 (D2-PAK) PHD71NQ03LT in SOT428 (D-PAK).
1.2 Features
s Logic level compatible s Low gate charge
1.3 Applications
s DC to DC converters s Switched mode power supplies
1.4 Quick reference data
s VDS = 30 V s Ptot = 120 W s ID = 75 A s RDSon 10 m
2. Pinning information
Table 1: 1 2 3 mb Pinning - SOT78, SOT404, SOT428 simplified outline and symbol Simplified outline
[1]
mb mb mb
Pin Description gate (g) drain (d) source (s) mounting base, connected to drain (d)
Symbol
d
g s
2 2 1
MBK106
MBB076
1 3
MBK116
3
MBK091
Top view
123
SOT78 (TO-220)
[1]
SOT404 (D2-PAK)
SOT428 (D-PAK)
It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
3. Limiting values
Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS VGSM ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) peak gate-source voltage drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 C peak source (diode forward) current Tmb = 25 C; pulsed; tp 10 s tp 50 s; pulsed; duty cycle = 25 % Tmb = 25 C; VGS = 10 V; Figure 2 and 3 Tmb = 100 C; VGS = 10 V; Figure 2 Tmb = 25 C; pulsed; tp 10 s; Figure 3 Tmb = 25 C; Figure 1 Conditions 25 C Tj 175 C 25 C Tj 175 C; RGS = 20 k Min -55 -55 Max 30 30 20 25 75 57.7 240 120 +175 +175 75 57.7 Unit V V V V A A A W C C A A
Source-drain diode
9397 750 09821
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
2 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
120 Pder (%) 80
03aa16
120 Ider (%) 80
03ai74
40
40
0 0 50 100 150 200 Tmb (C)
0 0 50 100 150 200 Tmb (C)
P tot P der = ---------------------- x 100% P
tot ( 25 C )
ID I der = ------------------- x 100% I
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of mounting base temperature.
Fig 2. Normalized continuous drain current as a function of mounting base temperature.
103 ID (A)
03ai76
Limit RDSon = VDS / ID
tp = 10 s
102
100 s
DC 10
1 ms
10 ms
1 1 10 VDS (V) 102
Tmb = 25 C; IDM is single pulse; VGS = 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09821
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
3 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
4. Thermal characteristics
Table 3: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ Max Unit 60 75 50 1.25 K/W K/W K/W K/W thermal resistance from junction to mounting base Figure 4 thermal resistance from junction to ambient SOT78 SOT428 SOT404 and SOT428 vertical in still air SOT428 minimum footprint; mounted on a PCB SOT404 minimum footprint; mounted on a PCB Symbol Parameter
4.1 Transient thermal impedance
10 Zth(j-mb) (K/W)
03ai75
1 = 0.5 0.2 0.1 10-1 0.05 0.02 single pulse 10-2 10-5 tp T 10-4 10-3 10-2 tp (s) 10-1 t P = tp T
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 09821
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
4 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
5. Characteristics
Table 4: Characteristics Tj = 25 C unless otherwise specified Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 C Tj = 175 C Tj = -55 C IDSS drain-source leakage current VDS = 30 V; VGS = 0 V Tj = 25 C Tj = 175 C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = 20 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 7 and 8 Tj = 25 C Tj = 175 C VGS = 10 V; ID = 25 A; Figure 7 Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 reverse recovery time recovered charge IS = 10 A; dIS/dt = -100 A/s; VGS = 0 V VDD = 15 V; ID = 25 A; VGS = 4.5 V; RG = 5.6 VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13 13.2 5.3 4.6 330 140 15 150 13.5 18 0.9 29 20 1.2 nC nC nC pF pF pF ns ns ns ns V ns nC 12 21.6 8 15.2 27.4 10 m m m 0.05 10 1 500 100 A A nA 1 0.6 1.9 2.5 2.9 V V V 30 27 V V Conditions Min Typ Max Unit
1220 -
Source-drain diode
9397 750 09821
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
5 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
80 ID (A) 60 Tj = 25 C
03ai77
80 ID (A) 60 VDS > ID x RDSon
03ai79
10 V 7 V 6 V 5.5 V 5V
4.5 V 40 4V 40
20
3.5 V
20 Tj = 25 C 4 6
VGS = 3 V 0 0 0.2 0.4 0.6 0.8 1 VDS (V) 0 0
175 C 2
VGS (V)
Tj = 25 C
Tj = 25 C and 175 C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values.
20 RDSon (m) 15 Tj = 25 C VGS = 4.5 V
03ai78
2 a 1.5
03af18
5V 5.5 V 6V 7V 10 V
10
1
5
0.5
0 0 20 40 60 ID (A) 80
0 -60 0 60 120 Tj (C) 180
Tj = 25 C
R DSon a = ---------------------------R DSon ( 25 C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature.
Fig 7. Drain-source on-state resistance as a function of drain current; typical values.
9397 750 09821
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
6 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
3.2 VGS(th) (V) max 2.4 typ 1.6
03ai29
10-1 ID (A) 10-2
03ai28
10-3
min
typ
max
10-4 min 0.8 10-5
0 -60 0 60 120 Tj (C) 180
10-6 0 0.8 1.6 2.4 VGS(V) 3.2
ID = 1 mA; VDS = VGS
Tj = 25 C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of junction temperature.
Fig 10. Sub-threshold drain current as a function of gate-source voltage.
104
03ai81
C (pF)
103
Ciss
Coss
102 10-1
Crss 1 10 VDS (V) 102
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
9397 750 09821
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
7 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
80 IS (A) 60 VGS = 0 V
03ai80
10 VGS (V) 8 ID = 50 A Tj = 25 C VDD = 15 V 6
03ai82
40 4
20 175 C Tj = 25 C
2
0 0 0.3 0.6 0.9 VSD (V) 1.2
0 0 5 10 15 20 25 QG (nC)
Tj = 25 C and 175 C; VGS = 0 V
ID = 50 A; VDD = 15 V
Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.
Fig 13. Gate-source voltage as a function of gate charge; typical values.
9397 750 09821
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
8 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
6. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78
E p
A A1 q
D1
mounting base
D
L1(1)
L2 Q
L
b1
1
2
3
b c
e
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.39 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.4 5.9 E 10.3 9.7 e 2.54 L 15.0 13.5 L1(1) 3.30 2.79 L2 max. 3.0 p 3.8 3.6 q 3.0 2.7 Q 2.6 2.2
Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC 3-lead TO-220AB EIAJ SC-46 EUROPEAN PROJECTION ISSUE DATE 00-09-07 01-02-16
Fig 14. SOT78 (TO-220AB).
9397 750 09821 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
9 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped)
SOT404
A E A1 mounting base
D1
D
HD
2
Lp
1
3
b c Q
e
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20
OUTLINE VERSION SOT404
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 99-06-25 01-02-12
Fig 15. SOT404 (D2-PAK)
9397 750 09821 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
10 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped)
SOT428
seating plane y A E b2 A A1 mounting base A2 E1
D1 D HE L2
2
L L1
1
b1 e e1 b
3
wM A c
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1(1) 0.65 0.45 A2 0.93 0.73 b 0.89 0.71 b1 1.1 0.9 b2 5.46 5.26 c 0.4 0.2 D 6.22 5.98 D1 min. 4.0 E 6.73 6.47 E1 e e1 HE 10.4 9.6 L 2.95 2.55 L1 min. 0.5 L2 0.9 0.5 w 0.2 y max. 0.2
4.81 2.285 4.57 4.45
Note 1. Measured from heatsink back to lead. OUTLINE VERSION SOT428 REFERENCES IEC JEDEC TO-252 JEITA SC-63 EUROPEAN PROJECTION ISSUE DATE 99-09-13 01-12-11
Fig 16. SOT428 (D-PAK)
9397 750 09821 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
11 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
7. Revision history
Table 5: Rev Date 01 20020625 Revision history CPCN Description Product data; initial version.
9397 750 09821
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
12 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
8. Data sheet status
Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] [2]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
9. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
10. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
11. Trademarks
TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 09821
Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 -- 25 June 2002
13 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOSTM logic level FET
Contents
1 1.1 1.2 1.3 1.4 2 3 4 4.1 5 6 7 8 9 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
(c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 25 June 2002 Document order number: 9397 750 09821

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